The solder bump interconnection was developed to eliminate the expense, unreliability, and low productivity of manual wire bonding. Solder bump interconnection technology for flip chip integrated circuits has been practiced in one form or another for approximately 20 years. Whereas the initial, low complexity integrated circuits typically had peripheral contacts, the flip chip bumping technology has allowed considerable increase in interconnect density as it progressed to full population area arrays. The controlled collapse chip connection utilizes solder bumps deposited on wettable metal terminals on the die and a matching footprint of solder wettable terminals on the substrate. The upside down integrated circuit (flip chip) is aligned to the substrate and all joints are made simultaneously by reflowing the solder. In the controlled collapse method, a bump of solder is deposited on the terminals of the integrated circuit. Numerous schemes to deposit a precisely formed solder bump on the die surface have been the subject of intense efforts over many years, with each solution to the problem having significant drawbacks. Even the best methods add substantial costs and processing steps to the die.
The solder bump is restrained from flowing out on the terminals by using thick film glass dams, limiting solder flow to the tip of the substrate metallization. Similarly, the flow of solder on the integrated circuit is limited by the size of the solderable pad on metal exposed in the covering surface of chemically vapor deposited glass passivation on the integrated circuit.
Selection of the solder alloy has been defined on the basis of melting point. High lead solders have been used when bonding the integrated circuit to alumina ceramic substrates because of the high melting point of the alloy, allowing further processing of the assembled circuit. Joining to organic carriers such as epoxy or polyimide circuit boards requires lower melting solder alloys. Solders such as eutectic tin/lead solder (melting point 183.degree. C.) or lead/indium solder (melting point 220.degree. C.) have been used.
The choice of terminal metallurgy depends on the solder selected. Silver and gold are poor choices since they rapidly dissolve in the solder. Thus, copper, tin, lead, palladium, platinum, or nickel are commonly used for the circuit board terminals, and chrome, titanium, or nickel thin films are commonly used for the integrated circuit terminal.
To join the integrated circuit to the substrate, a flux, either water-white rosin or water soluble flux, is placed on the substrate as a temporary adhesive to hold the integrated circuit in place. The assembly is subjected to a reflow thermal cycle, joining the die to the substrate in an oven or furnace. The surface tension of the solder aids to self align the die to the substrate terminals. After reflow, the flux residue must be removed in order to prevent corrosion of the die. Materials such as chlorinated, fluorinated or hydrocarbon solvents are used to remove the rosin, or water with surfactants is used to remove a water soluble flux. Due to the close proximity of the die to the substrate (typically 0.001 to 0.004 inches), removing the flux residue from under the die is a difficult operation requiring sophisticated cleaning regimes and a significant expenditure of time. Insuring complete removal of all flux residue has been the subject of much effort in the industry.
After cleaning, the assembly is electrically tested, and further packaging is added to provide environmental protection. Passivation, encapsulation, or addition of a cover are the usual methods. In the case of encapsulation, a liquid polymer is applied around and under the die. Historically, the polymers of choice have been silicones and epoxies, with epoxies finding greater favor. The adhesion of epoxies to a ceramic substrate is superior to silicones. The expansion coefficient of epoxies can be lowered with the addition of ceramic fillers. This reduces thermal stresses that develop between the substrate and the encapsulant. The importance of epoxy adhesives with low expansion coefficients cannot be over emphasized for flip chip applications. Cured epoxies are hard and do not posses the flexibility of silicones. Thus, if their expansion coefficients are not lowered with fillers, early device failure can result from crack formation in the die. The use of inorganic fillers also affects thermal conductivity and the level of ionic contaminants.
The very small gap between the die and the substrate must be completely filled in order to provide maximum environmental protection for the device. Previous efforts to seal the device left a voided area in the center of the die, as described in U.S. Pat. No. 4,604,644, where an organic resin is applied around the periphery of the die, and drawn into the space by capillary action. As the size of dies increase, the limiting effect of capillary action becomes more critical and leaves an even greater area of the die unprotected.
Other methods of encapsulating the die surface have attempted to overcome the above limitations by applying the organic resin through a hole in the substrate, located at the center of the die. After the soldering and cleaning operations, the encapsulating resin is applied through the hole and also around the periphery of the die, to insure complete coverage of the die surface. This method suffers from the need to reserve an area in the substrate that is free of circuitry, in order to provide a unused space for the hole.
Clearly, an improved method of encapsulating flip chip integrated circuits that eliminates solder bumping, insures complete coverage of the die surface, and allows maximum use of the available area of the substrate is needed.